PCM1792

SLES069B − MARCH 2003 − REVISED NOVEMBER 2006

www.ti.com

21

MSB

LSB

Register Index (or Address)

Register Data

R/W

IDX6

IDX5

IDX4

IDX3

IDX2

IDX1

IDX0

D7

D6

D4

D5

D3

D2

D1

D0

Figure 29. Control Data Word Format for MDI

High Impedance

When Read Mode is Instructed

A0

D7

D6

D4

D5

D3

D2

D1

D0

D7

D6

D4

D5

D3

D2

D1

D0

R/W

A1

A2

A3

A4

A5

A6

MS

MC

MDI

MDO

NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14−8 are used for the register

address. Bits 7–0 are used for register data.

Figure 30. Serial Control Format

t(MCH)

50% of VDD

MS

t(MSS)

LSB

50% of VDD

50% of VDD

t(MCL)

t(MHH)

t(MSH)

t(MCY)

t(MDH)

t(MDS)

MC

MDI

t(MOS)

50% of VDD

MDO

PARAMETER

MIN

MAX

UNITS

t(MCY) MC pulse cycle time

100

ns

t(MCL)

MC low-level time

40

ns

t(MCH) MC high-level time

40

ns

t(MHH) MS high-level time

80

ns

t(MSS)

MS falling edge to MC rising edge

15

ns

t(MSH) MS hold time(1)

15

ns

t(MDH) MDI hold time

15

ns

t(MDS) MDI setup time

15

ns

t(MOS) MC falling edge to MDO stable

30

ns

(1) MC rising edge for LSB to MS rising edge

Figure 31. Control Interface Timing