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PCM1792DB.B 데이터시트(PDF) 40 Page - Texas Instruments

부품명 PCM1792DB.B
상세설명  24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER
PDF  62 Pages
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제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

PCM1792DB.B 데이터시트(HTML) 40 Page - Texas Instruments

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PCM1792
SLES069B − MARCH 2003 − REVISED NOVEMBER 2006
www.ti.com
40
DATA
t(BCH)
50% of VDD
BCK
WDCK
(LRCK)
t(BCL)
t(LB)
t(BCY)
t(DS)
t(DH)
50% of VDD
50% of VDD
t(BL)
PARAMETER
MIN
MAX
UNITS
t(BCY) BCK pulse cycle time
20
ns
t(BCL) BCK pulse duration, LOW
7
ns
t(BCH) BCK pulse duration, HIGH
7
ns
t(BL)
BCK rising edge to WDCK falling edge
5
ns
t(LB)
WDCK falling edge to BCK rising edge
5
ns
t(DS)
DATA setup time
5
ns
t(DH)
DATA hold time
5
ns
Figure 42. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
Functions Available in the External Digital Filter Mode
The external digital filter mode allows access to the majority of the PCM1792 mode control functions.
The following table shows the register mapping available when the external digital filter mode is selected, along with
descriptions of functions which are modified when using this mode selection.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
−
−
−
−
−
−
−
−
Register 17
R/W
0
0
1
0
0
0
1
−
−
−
−
−
−
−
−
Register 18
R/W
0
0
1
0
0
1
0
−
FMT2
FMT1
FMT0
−
−
−
−
Register 19
R/W
0
0
1
0
0
1
1
REV
−
−
OPE
−
DFMS
−
INZD
Register 20
R/W
0
0
1
0
1
0
0
−
SRST
0
1
MONO
CHSL
OS1
OS0
Register 21
R/W
0
0
1
0
1
0
1
−
−
−
−
−
−
−
PCMZ
Register 22
R
0
0
1
0
1
1
0
−
−
−
−
−
−
ZFGR
ZFGL
NOTE: 1: Bit is required for selection of external digital filter mode.
−:Function is disabled. No operation even if data bit is set
FMT[2:0]: Audio Data Format Selection
Default value: 000
FMT[2:0]
Audio Data Format Select
000
16-bit right-justified format (default)
001
20-bit right-justified format
010
24-bit right-justified format
Other
N/A



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