PIC16F570 datasheet(29/134 Pages) MICROCHIP

29 / 134 page

 2012-2014 Microchip Technology Inc.

DS40001652C-page 29

PIC16F527

6.6

PORTA: PORTA REGISTER

TABLE 6-1:

PORTA PINS ORDER OF PRECEDENCE

TABLE 6-2:

WEAK PULL-UP ENABLED PINS

PORTB: PORTB REGISTER

TABLE 6-3:

PORTB PINS ORDER OF

PRECEDENCE

U-0

R/W-x

—

RA5

RA4

RA3

RA2

RA1

RA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’

bit 5-0

RA<5:0>: PORTA I/O Pin bits

1 = Port pin is >VIH min.

0 = Port pin is <VIL max.

Priority

RA5

RA4

RA3

RA2

RA1

RA0

OSC1

OSC2

RA3/MCLR

AN2

CVREF

AN0

2CLKIN

CLKOUT

—

C1OUT

AN1

C1IN+

TRISA5

AN3

—

T0CKI

C1IN-

TRISA0

—

TRISA4

—

TRISA2

TRISA1

—

Device

RA0 Weak Pull-up RA1 Weak Pull-up RA3 Weak Pull-up(1)

RA4 Weak Pull-up

PIC16F527

Yes

Note 1: When MCLRE = 1, the weak pull-up on MCLR is always enabled.

R/W-x

U-0

RB7

RB6

RB5

RB4

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

RB<7:4>: PORTB I/O Pin bits

1 = Port pin is >VIH min.

0 = Port pin is <VIL max.

bit 3-0

Unimplemented: Read as ‘0’

Priority

RB7

RB6

RB5

RB4

TRISB7 TRISB6

OP2+

OP2-

—

TRISB5

TRISB4

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