FN8808 datasheet(30/44 Pages) RENESAS

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ISL78227

FN8808 Rev.6.02

Page 30 of 43

Feb 28, 2025

occurs when starting up to a high pre-biased output voltage.

This feature makes the system robust for all the challenging

start-up conditions and greatly improves the system

reliability.

Enable

To enable the device, the EN pin needs to be driven higher than

1.2V (typical) by the external enable signal or resistor divider

between VIN and GND. The EN pin has an internal, 5MΩ (typical),

pull-down resistor. This pin also has an internal 5.2V (typical)

clamp circuit with a 5kΩ (typical) resistor in series to prevent

excess voltage applied to the internal circuits. When applying the

EN signal using resistor divider from VIN, internal pull-down

resistance needs to be considered. Also, the resistor divider ratio

needs to be adjusted as its EN pin input voltage may not exceed

5.2V.

To disable or reset all fault status, the EN pin needs to be driven

lower than 1.1V (typical). When the EN pin is driven low, the

ISL78227 turns off all of the blocks to minimize the off-state

quiescent current.

Soft-Start

Soft-start is implemented by an internal 5µA current source

charging the soft-start capacitor (CSS) at SS to ground. The

voltage on the SS pin slowly ramps up as the reference voltage

for the FB voltage to follow during soft-start.

Typically, for boost converter before soft-start, its output voltage

is charged up to be approximately a diode drop below the input

voltage through the upper side MOSFETs’ body diodes. To more

accurately correlate the soft-start ramp time to the output

voltage ramp time, the ISL78227 SS pin voltage is pre-biased

with voltage equal to FB voltage before soft-start begins. The

soft-start ramp time for the boost output voltage ramping from

VIN to the final regulated voltage VOUTreg, can be calculated by

Equation 7, where VREF is 1.6V (VREF_1.6V) with the TRACK pin

tied HIGH:

PGOOD Signal

The PGOOD pin is an open-drain logic output to indicate that the

soft-start period is completed, the input voltage is within safe

operating range, and the output voltage is within the specified

range. The PGOOD comparator monitors the FB pin to check if

the output voltage is within 80% to 120% of the reference

voltage VREF_1.6V.

As described at the t8 - t9 duration in “Operation Initialization

and Soft-Start” on page 29, the PGOOD pin is pulled low during

soft-start and it is released high after SS_DONE with a 0.5ms or

100ms delay.

PGOOD is pulled low if any of the comparators for FB_UV, FB_OV

or VIN_OV, is triggered for a duration longer than 10µs.

In normal operation after start-up, under fault recovery, PGOOD

is released high with the same 0.5ms delay time after the fault is

removed.

Current Sense

The ISL78227 peak current control architecture senses the

inductor current continuously for fast response. A sense resistor

is placed in series with the power inductor for each phase. The

ISL78227 Current Sense Amplifiers (CSA) continuously sense the

respective inductor current as shown in Figure 60 on page 31 by

sensing the voltage signal across the sense resistor, RSENx

(where “x” indicates the specific phase number and same note

applied throughout this document). The sensed current for each

active phase is used for peak current mode control loop, phase

current balance, individual phase cycle-by-cycle peak current

limiting (OC1), individual phase overcurrent fault protection

(OC2_PEAK), input average Constant Current (CC) control and

average overcurrent protection (OC_AVG), diode emulation, and

phase drop control. The internal circuitry shown in Figure 60

represents a single phase. This circuitry is repeated for each

phase.

FIGURE 59. ENABLE BLOCK

FROM

EXTERNAL

EN CONTROL

VCC

5.2V

CLAMP

1.2V

TO INTERNAL

CIRCUITS

VIN

(EQ. 7)

tSS VREF 1

VIN

VOUTreg

------------------------

–











 CSS

5A

-----------



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