| 전자부품 데이터시트 검색엔진 |
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FN8808 데이터시트(PDF) 7 Page - Renesas Technology Corp |
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FN8808 데이터시트(HTML) 7 Page - Renesas Technology Corp |
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7 / 44 page ![]() Block Diagram FIGURE 3. BLOCK DIAGRAM 5.2V LDO VIN PVCC VCC SS 1.2*VREF_1.6V 0.8*VREF_1.6V PGOOD Gm1 ATRK/DTRK VREF_1.6V FB COMP CLKOUT PLLCOMP FSYNC SLOPE R2 Q S R1 CSA ISEN1P ISEN1N BOOT1 UG1 PH1 LG1 DE/PHDRP DUPLICATE FOR EACH PHASE ISEN1 105µA OC2_PEAK_PH1 ISEN1 DROP_PHASE2 SGND (BOTTOM PAD) 5µA FAULT FAULT LOGIC PLLCOMP_SHORT VOUT_OV PVCC PGND PGND OC_AVG VREF_TRK DE MODE AND PHASE DROP MODE SELECTION IMON 2V OC_AVG Gm2 PROGRAMMABLE ADAPTIVE DEAD TIME RDT RBLANK HIC/LATCH LP Filter TRACK VREF_2.5V 1k M U X SS CLOCK VRAMP 80µA OC1_PH1 -48µA OC_NEG_PH1 ISEN1 ISEN1 2µA ISEN1 VCO PLL CLOCK SLOPE COMPENSATION VIN_OV OC2_PEAK_PH1 OC2_PEAK_PH2 ATRAK/ DTRK ÷ 48 POR 1.21V EN EN EN VIN/48 OTP PLL SOFT-START DELAYAND LOGIC EN_SS PWM CONTROL ZCD_PH1 17µA 3.47V VREF_TRK 0.3V SS HICCUP /LATCHOFF 1.1V PHASE_DROP VREF_CC(1.6V) 1.21V 112µA 112µA ÷ 8 ÷ 8 IOUT VIMON VFB VFB VIN_OV FAULT INITIALIZATION DELAY EN_DE PHASE DROP CONTROL EN_PHASE_DROP HICCUP RETRY DELAY LATCH-OFF LOGIC SS_DONE EN_HICCP EN_LATCHOFF ISEN1 ISEN2 (PHASE1) (PHASE2) PWM COMPARATOR CMP_PD CMP_OCAVG DCC VOUT_OV VOUT_UV DELAY EN PLL_LOCK + + + - + - + - + - + - |
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