6

CDCM1802

SCAS759C – APRIL 2004 – REVISED JULY 2017

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Copyright © 2004–2017, Texas Instruments Incorporated

(1)

For a 800-MHz signal, the 50-ps error would result into a duty cycle distortion of ±4% when driven by an ideal clock input signal.

(2)

For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of ±3% when driven by an ideal clock input signal.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVPECL OUTPUT DRIVER Y0, Y0

tDuty

Output duty cycle distortion(1)

Crossing point-to-crossing point

distortion

−50

50

ps

tsk(pp)

Part-to-part skew

Any Y0 (see Note A in Figure 7)

50

ps

tr/tf

Rise and fall time

20% to 80% of VOUTPP

(see Figure 8)

200

350

ps

LVPECL INPUT-TO-LVPECL OUTPUT PARAMETER

tpd(lh)

Propagation delay rising edge

VOX to VOX

320

600

ps

tpd(hl)

Propagation delay falling edge

VOX to VOX

320

600

ps

tsk(p)

LVPECL pulse skew

(see Note B in Figure 7)

VOX to VOX

100

ps

LVCMOS OUTPUT PARAMETER, Y1

tskLVCMOS(o)

Output skew between the LVCMOS

output Y1 and LVPECL output Y0

VOX to VDD / 2 (see Figure 7)

1.6

ns

tDuty

Output duty cycle distortion(2)

Measured at VDD / 2

−150

150

ps

tsk(pp)

Part-to-part skew

Y1 (see Note A in Figure 7)

300

ps

tpd(lh)

Propagation delay rising edge from

IN to Y1

VOX to VDD / 2 load (see Figure 9)

1.6

2.6

ns

tpd(hl)

Propagation delay falling edge from

IN to Y1

VOX to VDD / 2 load (see Figure 9)

1.6

2.6

ns

tr

Output rise slew rate

20% to 80% of swing

(see Figure 9)

1.4

2.3

V/ns

tf

Output fall slew rate

80% to 20% of swing

(see Figure 9)

1.4

2.3

V/ns

6.7 Jitter Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tjitterLVPECL

Additive phase jitter from input to

LVPECL output Y0

(see Figure 1)

12 kHz to 20 MHz, fout = 250 MHz to 800 MHz,

divide by 1 mode

0.15

ps rms

50 kHz to 40 MHz, fout = 250 MHz to 800 MHz,

divide by 1 mode

0.25

ps rms

tjitterLVCMOS

Additive phase jitter from input to

LVCMOS output Y1

(see Figure 2)

12 kHz to 20 MHz, fout = 250 MHz, divide by 1

mode

0.25

ps rms

50 kHz to 40 MHz, fout = 250 MHz, divide by 1

mode

0.4

ps rms

6.8 Supply Current Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IDD

Supply current

Full load

All outputs enabled and terminated with 50 Ω to VDD − 2 V on

LVPECL outputs and 10 pF on LVCMOS output,

f = 800 MHz for LVPECL outputs and 200 MHz for LVCMOS,

VDD = 3.3 V

100

mA

No load

Outputs enabled, no output load, f = 800 MHz for LVPECL outputs

and 200 MHz for LVCMOS, VDD = 3.6 V

85

mA

IDDZ

Supply current, 3-state

All outputs 3-state by control logic, f = 0 Hz, VDD = 3.6 V

0.5

mA