Clock Inputs

1000 W

~ 2.4 V

CLK

CLK

AVDD5

AVDD5

1000 W

GND

ADS5463/5474/54RF63

GND

GND

~ 2.5 nH Bond Wire

~ 2.5 nH Bond Wire

Parasitic

~0.8pF

Parasitic

~0.8pF

S0292-01

Internal

Clock

Buffer

~ 0.5pF

Package

~ 0.5pF

Package

~ 200fF

BondPad

~ 200fF

BondPad

CLK

ADS5463

CLK

SquareWaveor

SineWave

0.01 F

m

0.01 F

m

S0168-05

ADS5463

ADS54RF63

www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009

The ADS5463/ADS54RF63 clock input can be driven with either a differential clock signal or a single-ended clock

input. The equivalent clock input circuit can be seen in Figure 57. The 0.5 pF of parasitic package capacitance is

before soldering. When jitter may not be a big concern, the use of a single-ended clock (as shown in Figure 58)

could save cost and board space without much performance tradeoff. When clocked with this configuration, it is

best to connect CLK to ground with a 0.01-

µF capacitor, while CLK is ac-coupled with a 0.01-µF capacitor to the

clock source, as shown in Figure 58.

Figure 57. Clock Input Circuit (unsoldered package)

Figure 58. Single-Ended Clock

Copyright © 2006–2009, Texas Instruments Incorporated

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Product Folder Link(s): ADS5463 ADS54RF63