Clock Common Mode − V

60

65

70

75

80

85

0

1

2

3

4

5

fIN = 100 MHz

fIN = 300 MHz

G024

fS = 500 MSPS

Clock Common Mode − V

60

61

62

63

64

65

66

0

1

2

3

4

5

fIN = 100 MHz

fIN = 300 MHz

G025

fS = 500 MSPS

Duty Cycle − %

50

55

60

65

70

75

80

85

20

30

40

50

60

70

80

fS = 500 MSPS

G021

fIN = 100 MHz

fIN = 300 MHz

ADS5463

ADS54RF63

www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009

Figure 62. ADS5463 SFDR versus Clock Common Mode

Figure 63. ADS5463 SNR versus Clock Common Mode

Figure 64. ADS5463 SFDR vs Clock Duty Cycle

To understand how to determine the required clock jitter, an example is useful. The ADS5463 is capable of

achieving 63.6 dBFS SNR at 450 MHz of analog input frequency. In order to achieve this SNR at 450 MHz the

clock source rms jitter must be at least 181 fsec when combined with the 150 fsec of internal aperture jitter in

order for the total rms jitter to be 234 fsec. A summary of maximum recommended rms clock jitter as a function

of analog input frequency is provided in Table 2 (using 150 fsec of internal aperture jitter). The equations used to

create the table are also presented.

Copyright © 2006–2009, Texas Instruments Incorporated

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