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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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L9300 데이터시트(PDF) 129 Page - STMicroelectronics |
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L9300 데이터시트(HTML) 129 Page - STMicroelectronics |
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129 / 178 page  WDG2ANSTMG Q&A Answer Timing 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address: GLOBAL_BaseAddress + 0x10 Type: RW Reset: 0b0000 0011 0000 1111 1111 Description: Register contains answer timings parameters [19:14] Answer Time-out Delta: End of the period for answers acceptance. Once reached the WD_RST signal will be sent independently on the Error status (WD_CNT). The value specified is an incremental time starting from T_Valid_Answ_Start and T_Valid_Answ_End_Delta. Time = (T_Valid_Answ_Start + T_Valid_Answ_End_Delta + T_Answ_TimeOut_Delta) * WD_clk Reset events: VB_UV, GND_LOSS, POR [13:8] Valid Answer End Delta: End of the timing window inside which answers must be received. The value specified is an incremental time starting from T_Valid_Answ_Start. Time = (T_Valid_Answ_Start + T_Valid_Answ_End_Delta) * WD_clk Reset events: VB_UV, GND_LOSS, POR [7:0] Valid Answer Start: Start of the timing window inside which answers must be received. Absolute value. Time = T_Valid_Answ_Start * WD_clk Reset events: VB_UV, GND_LOSS, POR L9300 SPI interface and register mapping DS12258 - Rev 5 page 129/178 |
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