L9663 datasheet(61/106 Pages) STMICROELECTRONICS

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DS11401 Rev 6

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L9663

Communication interface

105

CH1_CR2 (PROG)

Channel 1 Configuration Register 2

Address:

010010

Type:

R/W

Description:

Default value:

010

100

010

R/W

[15:13] RESERVED

[12] CH1_BT1_DIS1: Bootstrap ch1 disable

0: enabled

1: disabled

[11] CH1_CRCP2: Parity or CRC in time slot 2

0: CRC

1: parity

[10:6] CH1_NOB2: Number of data bits in time slot 2

01000: 8 data bits

…

11100: 28 data bits

others: default (20 bit)

[5] CH1_CRCP1: Parity or CRC in time slot 1

0: CRC

1: parity

[4:0] CH1_NOB1: Number of data bits in time slot 1

01000: 8 data bits

…

11100: 28 data bits

others: default (20 bit)

Settings programmed for time slot 1 are automatically applied to the other time slots in case at least one of the

following conditions in CH1_CR1 register is verified:

– READ_INIT_DATA1='1'

– TSM1_SEL="10" (simple configuration)

– SYNC1_EN='0' (asynchronous mode)

Although the settings of time slot 1 are automatically applied by the logic to other time slots, these are not written in

the corresponding configuration registers. In order to avoid not up-to-date readout of the time slot configuration by

SPI and to prevent from wrong SPI errors in case of mismatches in the number of SPI transfers (refer to

Section 5.2.4

case 2), it is recommended to confirm the time slot 1 configuration also for the other times slots.

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