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L9924L 데이터시트(PDF) 49 Page - STMicroelectronics |
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L9924L 데이터시트(HTML) 49 Page - STMicroelectronics |
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49 / 84 page ![]() DocID028840 Rev 3 49/84 L9924L Watchdog 83 6 Watchdog In order to support system safety, the Smart Power logic provides an embedded windowed watchdog block able to operate either on the Smart Power analog blocks or on the microcontroller; this approach guarantees system control also when the microcontroller is not powered or doesn't work at all. A watchdog is a unit designed to reset the system if a refresh operation is not accomplished within a specified time window: if the refresh is not done at all or if it is done before or later, the unit switches the power stage off and, if suitably configured, resets the microcontroller. In this way the system is able to prevent either SW or HW errors: SW: the code flow is lost or in a deadlock HW: the microcontroller is stopped for any reason To handle the Smart Power watchdog the following parameters need to be defined: start window: – it is the time interval, after the last refresh, where the watchdog refresh cannot be accomplished. A refresh in this interval causes a watch dog error occurrence; this feature detects a condition where the code falls into a never ending loop including a refresh operation or an accelerated system clock operating window: – it is the time interval, after the start window, where the watchdog refresh must be accomplished. A refresh after this interval causes a watch dog error occurrence; this feature detects a condition where the code falls into a never ending loop excluding a refresh operation or a decelerated system clock windows resolution: – the watchdog timing resolution is configurable to better fit system needs refresh words: – to improve safety, when refreshing the watchdog, the system must alternate two different keywords Watchdog configuration and refresh are handled by the microcontroller by writing suitable data in the SPI watchdog registers [12.4.15] [12.4.19]. The following picture shows a timing diagram of watchdog behavior: Figure 22. Timing diagram of watchdog Once the watchdog has been correctly refreshed the above sequence restarts. |
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