DP83867CS datasheet(66/129 Pages) TI2

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7.6.20 BIST Control Register (BISCR)

This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random

Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact

loopback point in the signal chain is also done in this register.

Table 7-30. BIST Control Register (BISCR), Address 0x0016

BIT

BIT NAME

DEFAULT

DESCRIPTION

PRBS_COUNT_MODE

0, RW

PRBS Continuous Mode:

1 = Continuous mode enabled. When one of the PRBS counters

reaches the maximum value, a pulse is generated and the counter

starts counting from zero again. This bit must be set for proper PRBS

operation.

0 = PRBS continuous mode disabled. PRBS operation is not

supported for this setting.

GEN_PRBS_PACKET

0, RW

Generated PRBS Packets:

1 = When the packet generator is enabled, the PHY generates

continuous packets with PRBS data. When the packet generator is

disabled, the PRBS checker is still enabled.

0 = When the packet generator is enabled, the PHY generates a

single packet with constant data. PRBS generation and checking is

disabled.

PACKET_GEN_64BIT_MODE

0, RW

BIST Packet Size:

1 = Transmit 64 byte packets in packet generation mode.

0 = Transmit 1518 byte packets in packet generation mode

PACKET_GEN_EN

0, RW

Packet BIST Enable:

1 = Enable packet/PRBS generator

0 = Disable packet/PRBS generator

11:8

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

REV_LOOP_RX_DATA_CTRL

0, RW

Reverse Loopback Receive Data Control:

This bit can only be set in Reverse Loopback mode.

1 = Send RX packets to MAC in reverse loop

0 = Suppress RX packets to MAC in reverse loop

MII_LOOP_TX_DATA_CTRL

0, RW

MII Loopback Transmit Data Control:

This bit can only be set in MII Loopback mode.

1 = Transmit data to MDI in MII loop

0 = Suppress data to MDI in MII loop

5:2

LOOPBACK_MODE

0, RW

Loopback Mode Select:

PCS Loopback must be disabled (Bits [1:0] =00) prior to selecting the

loopback mode.

1000: Reverse loop

0100: External loop

0010: Analog loop

0001: Digital loop

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

www.ti.com

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