IS25LE01G-RILA3-TY datasheet(160/186 Pages) ISSI

부품명	IS25LE01G-RILA3-TY

상세설명	SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	186 Pages

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IS25LE01G

IS25WE01G

Integrated Silicon Solution, Inc.- www.issi.com

160

Rev. A6

01/14/2025

8.59 SET FREEZE BIT OPERATION (SFRZ, 91h)

The Set FREEZE Bit (SFRZ) command sets FREEZE (PPB Lock Register bit7) to one. Please refer to the section

6.6.3 PPB Lock Register for more detail. Before the SFRZ command can be accepted by the device, a Write Enable

(WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the

Status Register to enable any write operations.

The SFRZ command is entered by driving CE# low, followed by the instruction code. CE# must be driven high after

the eighth bit of instruction has been latched in. If not, the SFRZ command is not executed. As soon as CE# is

driven high, the SFRZ operation is initiated. While the SFRZ operation is in progress, the Status Register may still

be read to check the value of the Write

In Progress (WIP) bit. The WIP bit is “1” during the SFRZ operation, and is

“0” when it is completed. When the SFRZ operation is completed, the WEL is set to “0”.

Figure 8.130 Set FREEZE Bit Sequence In SPI Mode

Instruction = 91h

CE#

SCK

Mode 3

Mode 0

High Impedance

Figure 8.131 Set FREEZE Bit Sequence In QPI Mode

91h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

IS25LE01G-RILA3-TY 데이터시트(PDF) 160 Page - Integrated Silicon Solution, Inc