전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

CC115LRGPR 데이터시트(PDF) 47 Page - Texas Instruments

부품명 CC115LRGPR
상세설명  CC115L Value Line Transmitter
PDF  74 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

CC115LRGPR 데이터시트(HTML) 47 Page - Texas Instruments

Back Button CC115LRGPR Datasheet HTML 43Page - Texas Instruments CC115LRGPR Datasheet HTML 44Page - Texas Instruments CC115LRGPR Datasheet HTML 45Page - Texas Instruments CC115LRGPR Datasheet HTML 46Page - Texas Instruments CC115LRGPR Datasheet HTML 47Page - Texas Instruments CC115LRGPR Datasheet HTML 48Page - Texas Instruments CC115LRGPR Datasheet HTML 49Page - Texas Instruments CC115LRGPR Datasheet HTML 50Page - Texas Instruments CC115LRGPR Datasheet HTML 51Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 47 / 74 page
background image
CC115L
www.ti.com
SWRS105B – MAY 2011 – REVISED JUNE 2014
Table 5-16. SPI Address Space (continued)
Write
Read
Single Byte
Burst
Single Byte
Burst
+0x00
+0x40
+0x80
+0xC0
0x30
SRES
SRES
PARTNUM
0x31
SFSTXON
SFSTXON
VERSION
0x32
SXOFF
SXOFF
Reserved
0x33
SCAL
SCAL
Reserved
0x34
Not Used
Reserved
Reserved
0x35
STX
STX
MARCSTATE
0x36
SIDLE
SIDLE
Reserved
0x37
Reserved
Reserved
Reserved
0x38
Reserved
Reserved
PKTSTATUS
0x39
SPWD
SPWD
Reserved
0x3A
Reserved
Reserved
TXBYTES
0x3B
SFTX
SFTX
Reserved
0x3C
Reserved
Reserved
Reserved
0x3D
SNOP
SNOP
Reserved
0x3E
PATABLE
PATABLE
PATABLE
PATABLE
0x3F
TX FIFO
TX FIFO
Reserved
Reserved
5.19.1 Configuration Register Details - Registers with preserved values in SLEEP state
Table 5-17. 0x00: IOCFG2 - GDO2 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
R0
Not used
6
GDO2_INV
0
R/W
Invert output, that is, select active low (1) / high (0)
5:0
GDO2_CFG[5:0]
41 (101001)
R/W
Default is CHP_RDYn (see Table 5-12).
Table 5-18. 0x01: IOCFG1 - GDO1 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
Set high (1) or low (0) output drive strength on the GDO
7
GDO_DS
0
R/W
pins.
6
GDO1_INV
0
R/W
Invert output, that is, select active low (1) / high (0)
5:0
GDO1_CFG[5:0]
46 (101110)
R/W
Default is 3-state (see Table 5-12).
Table 5-19. 0x02: IOCFG0 - GDO0 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
0
R/W
Use setting from SmartRF Studio
6
GDO0_INV
0
R/W
Invert output, that is, select active low (1) / high (0)
Default is CLK_XOSC/192 (see Table 5-12).
5:0
GDO0_CFG[5:0]
63 (0x3F)
R/W
It is recommended to disable the clock output in
initialization, in order to optimize RF performance.
Copyright © 2011–2014, Texas Instruments Incorporated
Detailed Description
47
Submit Documentation Feedback
Product Folder Links: CC115L



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com