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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LLCC68 데이터시트(PDF) 102 Page - Semtech Corporation |
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LLCC68 데이터시트(HTML) 102 Page - Semtech Corporation |
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102 / 111 page  LLCC68 Data Sheet Rev. 1.1 DS.LLCC68.W.APP Dec 2024 102 of 111 Semtech LLCC68 www.semtech.com 15. Known Limitations This section summarizes the known limitations of the LLCC68 chips, and the related workarounds. 15.1 Modulation Quality with 500kHz LoRa Bandwidth 15.1.1 Description Some sensitivity degradation may be observed on any LoRa device, when receiving signals transmitted by the LLCC68 with a LoRa BW of 500kHz. 15.1.2 Workaround Before any packet transmission, bit #2 at address 0x0889 shall be set to: • 0 if the LoRa BW = 500kHz • 1 for any other LoRa BW • 1 for any (G)FSK configuration The following pseudo-code can be used before each packet transmission, to properly configure the chip: |
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