LLCC68 datasheet(104/111 Pages) SEMTECH

104 / 111 page

LLCC68

Data Sheet

Rev. 1.1

DS.LLCC68.W.APP

Dec 2024

104 of 111

Semtech

LLCC68

www.semtech.com

15.3 Implicit Header Mode Timeout Behavior

15.3.1 Description

When receiving LoRa packets in Rx mode with Timeout active, and no header (Implicit Mode), the timer responsible for generating the

Timeout (based on the RTC timer) is not stopped on RxDone event. Therefore, it may trigger an unexpected timeout in any subsequent mode

where the RTC isn’t re-invoked, and therefore reset and re-programmed.

15.3.2 Workaround

It is advised to add the following commands after ANY Rx with Timeout active sequence, which stop the RTC and clear the timeout event, if

any. The register at address 0x0902 is used to stop the counter, while the register at address 0x0944 clears the potential event.

The following pseudo-code can be used as a reference to implement the fix:

15.4 Optimizing the Inverted IQ Operation

15.4.1 Description

When exchanging LoRa packets with inverted IQ polarity, some packet losses may be observed for longer packets.

15.4.2 Workaround

Bit 2 at address 0x0736 must be set to:

• “0” when using inverted IQ polarity (see the SetPacketParam(...) command)

• “1” when using standard IQ polarity

The following pseudo-code can be used as a reference to implement the fix:

LLCC68 데이터시트(PDF) 104 Page - Semtech Corporation