PCI11010C datasheet(17/46 Pages) MICROCHIP

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2025 Microchip Technology Inc. and its subsidiaries

DS00006232A-page 17

PCI11010C

RMII (10/100 PHY) Pins

RMII Carrier

Sense (CRS)

and

RX Data Valid

(RX_DV)

RMII_CRS_DV

RGMII_I

Multiplexed on alternate clock cycles. In 10 Mbit/s

mode, it alternates every 10 clock cycles.

Note: This pin function is muxed with SGMII_RXP.

RMII 50 MHz

Reference Clock

(in)

RMII_REF_CLK_IN

RGMII_I

Reference clock may be an input on both devices

from an external clock source, or may be driven from

the MAC to the PHY, or may be driven from the PHY

to the MAC.

Note: This signal can be shared with an input-only

programmable pin function.

Note: This pin function is muxed with SGMII_RXM.

RMII Receive

Data 0

RMII_RXD0

RGMII_I

RMII Receive Data 0. The PHY transfers data to the

MAC using this signal.

Note: This signal can be shared with an input-only

programmable pin function.

Note: This pin function is muxed with SGMII_TXP.

RMII Receive

Data 1

RMII_RXD1

RGMII_I

RMII Receive Data 1. The PHY transfers data to the

MAC using this signal.

Note: This signal can be shared with an input-only

programmable pin function.

Note: This pin function is muxed with SGMII_TXM.

RMII Receive

Error

RMII_RX_ER

RGMII_I

RMII Receive error.

Note: This pin function is muxed with SGMII_-

CLKM.

RMII 50 MHz

Reference Clock

(out)

RMII_REF_CLK_OUT

RGMII_O

Reference clock may be an input on both devices

from an external clock source, or may be driven from

the MAC to the PHY, or may be driven from the PHY

to the MAC.

Note: This signal can be shared with an input-only

programmable pin function.

Note: This pin function is muxed with SGMII_CLKP.

RMII Transmit

Control

RMII_TX_EN

RGMII_O

Indicates the transmit data enable (TXEN) function

per the RMII specification.

RMII Transmit

Data 0

RMII_TXD0

RGMII_O

RMII Transmit Data 0. The MAC transmits data to the

PHY using this signal.

RMII Transmit

Data 1

RMII_TXD1

RGMII_O

RMII Transmit Data 1. The MAC transmits data to the

PHY using this signal.

SGMII+ (10/100/1000/2.5G PHY) Pins

SGMII+

Receive Data+

SGMII_RXP

SGMII_I

SGMII+ Receive Data+

Note: This pin function is muxed with RGMII_RX-

_CTL.

TABLE 3-2:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer Type

Description

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