MPF0900AMBA2ES datasheet(24/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

When the state machine enters the fail-safe transition, the FS_CNT[3:0] is compared and increased; if

FS_CNT[3:0] reaches the maximum count, the device will move directly to the Deep Fail-safe state and wait for

a valid condition to exit the state.

11.2.11 Deep Fail-safe (DFS) state

The DFS state is intended to work as a temporary lockdown state upon a cyclic critical failure condition.

Because the system may land in the DFS state and remain there indefinitely, the DFS state is designed to

consume as little current as possible, with just the minimum blocks enabled to perform the operations defined in

this state.

The maximum number of times the device can pass through the Fail-safe transition continuously prior to moving

into the DFS state is programmed using the OTP_MAX_FS_CNT[3:0] bits.

When OTP_MAX_FS_CNT[3:0] = 0x00, the DFS state will be disabled and the FSM will not be able to enter

this state by means of the fault counting mechanism, however more critical failures such as the temporary loss

of VIN or VANA, or other safety-critical failures, may still result in the transition to the DFS state to ensure the

system operates only under controlled safe conditions.

When the OTP_MAX_FS_CNT[3:0] != 0x00 and the FS_CNT [3:0] = OTP_MAX_FS_CNT [3:0], the device will

enter the DFS state.

FS_CNT[3:0] can be cleared manually during the SYSTEM ON states, or by a number of good watchdog

refreshes when WD_OK_FDC[2:0] != 0x00.

In this state, the PGOOD and RSTB pins remain asserted low all the time.

In devices targeting high safety integrity levels where the FS0B is operating in Active Safe-state mode, the

FS0B pin will remain asserted low during the DFS state.

For QM or devices targeting low safety integrity levels where the FS0B is operating in Fault status mode, the

FS0B will be asserted if the FS0B_DFS = 1, or another fault caused it to assert previously.

During DFS state, the VAON regulator will be disabled regardless of the operating mode, as well as all other

system regulators to prevent further damage to the system.

The PF09 provides various mechanisms to exit the DFS state, either requested externally via the PWRON

pin or generated automatically by the auto retry timer. One or more mechanisms to exit the DFS state are

selectable via the OTP registers during the device customization stage.

The OTP_PWRON_DFS bit is provided to allow the device to wake up from the DFS state via the PWRON pin.

OTP_PWRON_DFS

Description

PWRON is not able to exit DFS

PWRON able to exit DFS

Table 15. OTP_PWRON_DFS bit

The OTP_RETRY_DFS bit is provided to allow the device to wake up from the DFS state via the auto retry

timer.

OTP_RETRY_DFS

Description

Auto retry Disabled

Auto retry Enabled

Table 16. OTP_RETRY_DFS bit

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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