MPF0900AMBA2ES datasheet(53/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

The reaction to an OV/UV condition is defined by the OTP_VAON_FMODE bit:

When OTP_VAON_FMODE = 0 the VAON reacts in “notification mode” upon an OV/UV condition.

When OTP_VAON_FMODE = 1 the VAON reacts in “Reset mode” upon an OV/UV.

When the VAON reaction is set to notification mode, the block follows similar protection rules as defined in the

fault management for the system regulators:

• OV/UV Interrupt flag is set and the INTB pin asserted if the interrupt is not masked.

• PGOOD is asserted if OV/UV condition is not bypassed and VAON_PG_EN = 1.

• Fault counter is increased if OV/UV condition is not bypassed.

• Global fault timer is started if OV/UV condition is not bypassed.

• The FS0B pin will be asserted as defined by the pin configuration.

If the VAON fault reaction is set to notification mode, the VAON regulator will not be turned off internally when a

hard fault is detected and the device starts a power-down sequence.

When the VAON fault reaction is set to RESET mode, an OV/UV fault condition can start the following protective

mechanism:

• The OV/UV Interrupt flag is set and the INTB pin asserted if the interrupt is not masked.

• PGOOD is asserted if the OV/UV condition is not bypassed and VAON_PG_EN = 1.

• Fault counter is increased if the OV/UV condition is not bypassed.

• The FS0B pin will be asserted as defined by the pin configuration.

The dedicated VAON fault timer is started if the OV/UV condition is not bypassed, and the PMIC will require the

fault to be acknowledged to prevent a total system shutdown.

When the VAON fault reaction is set to RESET mode, a dedicated fault timer is provided to allow the system to

acknowledge an OV/UV fault before the VAON fault timer is expired. The MCU must acknowledge the OV/UV

fault on the VAON regulator by clearing the corresponding VAON_OV_I or VAON_UV_I interrupt flags.

If the fault condition is still present by the time the VAON_OV_I or VAON_UV_I flags are cleared, the flag will be

set again right away and the VAON fault timer is restarted.

The default duration of the VAON fault timer is set via the OTP_VAON_TFLT[2:0] bits and it can be modified

during the system-on states via the VAON_TFLT[2:0] bits.

VAON_TFLT [2:0]

VAON fault timer

000

500 us

001

1 ms

010

2 ms

011

5 ms

100

10 ms

101

25 ms

110

50 ms

111

100 ms

Table 52. VAON fault timer duration

In RESET mode, a current limit condition in the VAON regulator will not start the VAON fault timer, however, an

UV condition generated due to a current limit protection will be able to start the VAON fault timer and start a full

PMIC reset if the condition is not corrected.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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