MPF0900AMBA2ES datasheet(27/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

In Debug mode, the following conditions are valid:

• I2C communication uses standard communication, with no CRC and secure write disabled

• The default I2C address is 0x08, regardless of the address configured by OTP

• Watchdog operation/monitoring is disabled

• Secure write is disabled

• XRESET pin is disabled

• FCCU is disabled

• DVSMIN and DVSMAX limits are disabled

The PF09 can operate normally using the Debug mode configuration, as long as VIN does not go below the

UVDET threshold. If VIN is lost (VIN < UVDET) the mirror registers will be reset, and Debug mode configuration

must be performed again.

The DBG_MODE flag is provided to indicate the device is in Debug mode.

DBG_MODE

Debug mode

Disabled

Enabled

Table 21. Sys_Diag (register 0x82 )

11.2.12.1.1 Test mode

The device is able to operate in TEST mode. In TEST mode, the system shall be able to access the OTP mirror

registers as well as all registers needed for OTP programming.

In TEST mode, the following conditions are valid:

• I2C communication uses standard communication, with no CRC and secure write disabled

• The default I2C address is 0x08, regardless of the address configured by OTP

• Watchdog operation/monitoring is disabled

• Secure write is disabled

• XRESET pin is disabled

• FCCU is disabled

• DVSMIN and DVSMAX limits are disabled

11.2.12.1.1.1 OTP emulation

OTP Emulation mode allows the user to modify OTP mirror registers before powering up. This facilitates

exercising different features of the PF09 while deciding on the best configuration for a given application. This is

especially useful when optimizing the SWx compensation for the desired transient response.

In emulation mode, only a VIN < UVDET or a critical DMS fault condition sends the device into the DFS state

and causes a fuse reload upon exiting the DFS state.

11.2.12.1.1.2 OTP fuse programming

OTP fuse burning is performed in the DBGOFF state.

To burn the OTP fuses, devices must enter Test mode and write the desired values in the mirror registers.

Once the proper configuration is set on the mirror registers, the device is configured.

The programming command is executed while VDDOTP has a programming voltage between 7.5 V < VDDOTP

< 8.5 V.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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