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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LAN8818D/KDX 데이터시트(PDF) 55 Page - Microchip Technology |
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LAN8818D/KDX 데이터시트(HTML) 55 Page - Microchip Technology |
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55 / 101 page  LAN8818D © 2026 Microchip Technology Inc. and its subsidiaries DS00005832C-page 55 5.14 Loopbacks The device supports the following loopback operations to verify analog and/or digital paths: • Digital (Near-End) Loopback • Remote (Far-End) Loopback • External Connector Loopback • QSGMII/Q-USGMII Loopback All loopbacks are enabled on an individual per-port basis. 5.14.1 DIGITAL (NEAR-END) LOOPBACK This loopback mode checks the QSGMII/Q-USGMII transmit and receive data paths between the device and the exter- nal MAC, and is supported for all three speeds (10/100/1000 Mbps) at full-duplex. The loopback data path is shown in Figure 5-9. 1. QSGMII/Q-USGMII MAC transmits frames to the device. 2. Frames are wrapped around inside the device. 3. The device transmits frames back to QSGMII/Q-USGMII MAC. 5.14.2 REMOTE (FAR-END) LOOPBACK This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive data paths between the device and its link partner, and is supported for 1000BASE-T full-duplex mode only. The loopback data path is shown in Figure 5-10. 1. The Gigabit PHY link partner transmits frames to the device. 2. Frames are wrapped around inside the device. 3. The device transmits frames back to the Gigabit PHY link partner. FIGURE 5-9: DIGITAL (NEAR-END) LOOPBACK FIGURE 5-10: REMOTE (FAR-END) LOOPBACK PCS PMA LAN8818D MAC Switch or SoC Link Partner GPHY Port X PCS1G Port X PCS1G PCS1G PCS1G Other Ports MAC MAC MAC Port X QSGMII/Q-USGMII PCS PMA LAN8818D MAC Switch or SoC Link Partner GPHY Port X PCS1G Port X PCS1G PCS1G PCS1G Other Ports MAC MAC MAC Port X QSGMII/Q-USGMII |
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