STA328

16/41

Figure 13.

7.3.1

Delay Serial Clock Enable

7.3.2

Channel Input Mapping

Each channel received via I2S can be mapped to any internal processing channel via the Channel Input

Mapping registers. This allows for flexibility in processing. The default settings of these registers map

each I2S input channel to its corresponding processing channel.

7.4 CONFIGURATION REGISTER C (Address 02h)

7.4.1

The DDX® Power Output Mode selects how the DDX® output timing is configured. Different power de-

vices can use different output modes. The DDX-2060/2100/2160 recommended use is OM = 10. When

OM=11 the CSZ bits determine the size of the DDX® compensating pulse.

BIT

R/W

RST

NAME

DESCRIPTION

5

R/W

0

DSCKE

Delay Serial Clock Enable:

0 – No serial clock delay

1 – Serial clock delay by 1 core clock cycle to tolerate

BIT

R/W

RST

NAME

DESCRIPTION

6R/W

0

C1IM

7R/W

1

C2IM

D7

D6

D5

D4

D3

D2

D1

D0

CSZ4

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

10

000

1

0

BIT

R/W

RST

NAME

DESCRIPTION

1...0

R/W

10

OM (1...0)

DDX Power Output Mode:

BICKI

T0

T1

LRCKI

T2

T3

SDI

T4

T5