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8.11 Variable Max Power Correction (Address 27h-28h):

MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place

of the default coefficient when MPCV = 1.

Table 35.

8.12 Fault Detect Recovery (Address 2Bh-2Ch):

FDRC bits specify the 16-bit Fault Detect Recovery time delay. When FAULT is asserted, the TRISTATE

output will be immediately asserted low and held low for the time period specified by this constant. A con-

stant value of 0001h in this register is ~.083ms. The default value of 000C specifies ~.1mSec.

Table 36.

Figure 16.

D7

D6

D5

D4

D3

D2

D1

D0

MPCC15

MPCC14

MPCC13

MPCC12

MPCC11

MPCC10

MPCC9

MPCC8

00

10

11

0

1

MPCC7

MPCC6

MPCC5

MPCC4

MPCC3

MPCC2

MPCC1

MPCC0

11

00

00

0

0

D7

D6

D5

D4

D3

D2

D1

D0

FRDC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

000000

00

D7

D6

D5

D4

D3

D2

D1

D0

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

000011

00

Low current dead time = MAX(DTr,DTf)

OUTY

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

t

DTf

DTr

Duty cycle = 50%

INY

OUTY

gnd

+Vcc

M58

M57

R 8

Ω

+

-

V67 =

vdc = Vcc/2

D02AU1448