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STA027 데이터시트(PDF) 16 Page - STMicroelectronics |
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STA027 데이터시트(HTML) 16 Page - STMicroelectronics |
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16 / 44 page ![]() 5 Register description STA027 16/44 CD00066274 Description : This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz 5.2.4 PLL_AUDIO_XDIV_192 : Address : 0xDF (223) Type : RW - DEC Software Reset : 3 Description : This register must contain a XDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz 5.2.5 PLL_AUDIO_MDIV_192 : Address : 0xE0 (224) Type : RW - DEC Software Reset : 12 Description : This register must contain a MDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 |
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