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STA027 데이터시트(PDF) 17 Page - STMicroelectronics |
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STA027 데이터시트(HTML) 17 Page - STMicroelectronics |
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17 / 44 page ![]() STA027 5 Register description CD00066274 17/44 5.2.6 PLL_AUDIO_PEL_176 : Address : 0xE1 (225) Type : RW - DEC Software Reset : 54 Description : This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : –fact == 256 – external crystal provide a CRYCK running at 14.31818 MHz 5.2.7 PLL_AUDIO_PEH_176 : Address : 0xE2 (226) Type : RW - DEC Software Reset : 118 Description : This register must contain a PEH value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : – ofact == 256 – external crystal provide a CRYCK running at 14.31818 MHz 5.2.8 PLL_AUDIO_NDIV_176 : Address : 0xE3 (227) Type : RW - DEC Software Reset : 0 Description : This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 |
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