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STA027 데이터시트(PDF) 22 Page - STMicroelectronics |
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STA027 데이터시트(HTML) 22 Page - STMicroelectronics |
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22 / 44 page ![]() 5 Register description STA027 22/44 CD00066274 5.3.10 PLL_SYSTEM_MDIV_42_5 : Address : 0xEA (234) Type : RW - DEC Software Reset : 10 Description : This register must contain a MDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : – external crystal provide a CRYCK running at 14.31818 MHz 5.4 I2Sout_CONFIGURATION registers description 5.4.1 OUTPUT_CONF : Address : 0x66 (102) Type : RW - DEC Software Reset : 0 Description : If set to 1 enable the configurability of the PCM-BLOCK Output thanks to following registers, else disable this configurability and take embedded default configuration for PCM-BLOCK registers. Note that this embedded default configuration can be retrieved by user thanks to following setting : –PCM_DIV = 3; –PCM_CONF = 0; – PCM_CROSS = 0; 5.4.2 PCM_DIV : Address : 0x67 (103) Type : RW - DEC b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 DV5 DV4 DV3 DV2 DV1 DV0 |
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