MPC8313E datasheet(80/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

System Design Information

3. There is a PLL for the SerDes block.

21.2

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,

AVDD2, and SDAVDD respectively). The AVDD level should always be equivalent to VDD, and preferably

these voltages are derived directly from VDD through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits as illustrated in Figure 43, one to each of the five AVDD pins. By

providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the

other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD

pin, which is on the periphery of package, without the inductance of vias.

Figure 43 shows the PLL power supply filter circuits.

Figure 43. PLL Power Supply Filter Circuit

The SDAVDD signal provides power for the analog portions of the SerDes PLL. To ensure stability of the

internal clock, the power supplied to the PLL is filtered using a circuit like the one shown in Figure 44.

For maximum effectiveness, the filter circuit should be placed as closely as possible to the SDAVDD ball

to ensure it filters out as much noise as possible. The ground connection should be near the SDAVDD ball.

The 0.003-µF capacitor is closest to the ball, followed by the two 2.2-µF capacitors, and finally the 1-

resistor to the board supply plane. The capacitors are connected from traces from SDAVDD to the ground

plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be

kept short, wide, and direct.

Figure 44. SerDes PLL Power Supply Filter Circuit

VDD

AVDD1 and AVDD2

2.2 µF

Low ESL Surface Mount Capacitors

XCOREVDD

SDAVDD

2.2 µF1

0.003 µF

1. An 0805 sized capacitor is recommended for system initial bring-up.

SDAVSS

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