DIA1412

Version 1.0, Jul 2024

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25

17h

1.0066

27h

1.0278

37h

1.0486

Note:

(1) When measuring a 65 nm Intel CPU, the Ideality Setting should be the default 12h. When measuring a 45 nm Intel CPU, the

Ideality Setting should be 15h.

12.14. High Limit status register

In the interrupt mode, the High Limit status register indicates if the measured temperature of a certain channel

exceeds the High Limit for the programmed number of times in a consecutive measurements. Reading from the

High Limit status register will clear all bits. And the HIGH status bit in the status register will also be cleared.

In the comparator mode, the High Limit status register indicates if the measured temperature of a certain

channel exceeds the High Limit for the programmed number of times in a consecutive measurements. Once any

of the High Limit status bit is set, it will remain set until the measured temperatures drop below the High Limit

minus the Therm Hysteresis. Reading from the High Limit status register will not clear all bits.

In both interrupt mode and comparator mode, the HIGH status bit in the status register will be set if any of the

High Limit status bit is set. The HIGH status bit in the status register will be cleared when all the individual

channel High Limit status bits are cleared.

Addr.

Type

Register

B7

B6

B5

B4

B3

B2

B1

B0

Default

35h

R-C

High Limit status

Reserved

EHIGH

IHIGH

00h

Note: R-C = Read then Clear.

Bit

Name

Description

7:2

Reserved

Do not use.

1

EHIGH

This bit is set when the external channel exceeds its programmed High Limit.

0

IHIGH

This bit is set when the internal channel exceeds its programmed High Limit.

12.15. Low Limit status register

In the interrupt mode, the Low Limit status register indicates if the measured temperature of a certain channel

drops below the Low Limit for the programmed number of times in a consecutive measurements. Reading from

the Low Limit status register will clear all bits. And the Low status bit in the status register will also be cleared.

The LOW status bit in the status register will be set if any of the LOW status bit is set.

Addr. Type

Register

B7

B6

B5

B4

B3

B2

B1

B0

Default

36h

R-C

Low Limit status

Reserved

ELOW

ILOW

00h

Note: R-C = Read then Clear.