DIA1412CMP8 datasheet(8/34 Pages) DIOO

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DIA1412

Version 1.0, Jul 2024

www.dioo.com

ILEAK

Leakage current

______

ALERT and

______

THERM/ADDR pins

device powered or unpowered

TA < 85°C

pull-up voltage ≤ 3.6 V

±5

µA

SMBus interface

VIH

Input high voltage

5 V tolerant

2.0

VDD

VIL

Input low voltage

5 V tolerant

-0.3

0.8

ILEAK

Leakage current

Powered or unpowered, TA < 85°C

±5

µA

VHYS

Hysteresis

420

CIN

Input capacitance

IOL

Output low sink current

SMDATA = 0.4 V

8.2

SMBus timing (1, 2)

fsmb

Clock frequency

400

kHz

tSP

Spike suppression

tBUF

Bus free time stop to start

1.3

µs

tHD:STA

Hold time: start

0.6

µs

tSU:STA

Setup time: start

0.6

µs

tSU:STO

Setup time: stop

0.6

µs

tHD:DAT

Data hold time

When transmitting to the master

µs

When receiving from the master

0.3

tSU:DAT

Data setup time

100

tLOW

Clock low period

1.3

µs

tHIGH

Clock high period

0.6

µs

tFALL

Clock/data fall time

Min. = 20 + 0.1CLOAD ns

300

tRISE (1)

Clock/data rise time

Min. = 20 + 0.1CLOAD ns

300

CLOAD

Capacitive load

Per bus line

400

SMBus timeout (1)

ttimeout

Device will reset if SMCLK

is hold low for more than

Ttimeout

Note:

(1) Guaranteed by digital design.

(2) See figure 1.

(3) Specifications subject to change without notice.

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