M58BW016DB datasheet(40/63 Pages) STMICROELECTRONICS

40 / 63 page

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

40/63

Table 20. Synchronous Burst Read AC Characteristics

Note: 1. Data output should be read on the valid clock edge.

2. For other timings see Table 16, Asynchronous Bus Read Characteristics.

Figure 15. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge)

Note: For set up signals and timings see Synchronous Burst Read.

Symbol

Parameter

Test Condition

M58BW016

Unit

100

tAVLL

Address Valid to Latch Enable Low

E = VIL

Min

tBHKH

Burst Address Advance High to Valid Clock

Edge

E = VIL, G = VIL,

L = VIH

Min

tBLKH

Burst Address Advance Low to Valid Clock

Edge

E = VIL, G = VIL,

L = VIH

Min

tELLL

Chip Enable Low to Latch Enable low

Min

tGLQV

Output Enable Low to Output Valid

E = VIL, L = VIH

Min

tKHAX

Valid Clock Edge to Address Transition

E = VIL

Min

tKHLL

Valid Clock Edge to Latch Enable Low

E = VIL

Min

tKHLX

Valid Clock Edge to Latch Enable Transition

E = VIL

Min

tKHQX

Valid Clock Edge to Output Transition

E = VIL, G = VIL,

L = VIH

Min

tLLKH

Latch Enable Low to Valid Clock Edge

E = VIL

Min

tQVKH

(1)

Output Valid to Valid Clock Edge

E = VIL, G = VIL,

L = VIH

Min

tRLKH

Valid Data Ready Low to Valid Clock Edge

E = VIL, G = VIL,

L = VIH

Min

tKHQV

Valid Clock Edge to Output Valid

E = VIL, G = VIL,

L = VIH

Max

AI04408b

n+5

n+4

n+3

n+2

n+1

DQ0-DQ31

tQVKH

tKHQX

SETUP

Burst Read

Q0 to Q3

tKHQV

Note: n depends on Burst X-Latency

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