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M58BW016DB 데이터시트(PDF) 41 Page - STMicroelectronics |
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M58BW016DB 데이터시트(HTML) 41 Page - STMicroelectronics |
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41 / 63 page ![]() 41/63 M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 16. Synchronous Burst Read - Continuous - Valid Data Ready Output Note: Valid Data Ready = Valid Low during valid clock edge 1. V= Valid output. 2. R is an open drain output with an internal pull up resistor of 1M Ω. The internal timing of R follows DQ. An external resistor, typically 300k Ω. for a single memory on the R bus, should be used to give the data valid set up time required to recognize that valid data is available on the next valid clock edge. Figure 17. Synchronous Burst Read - Burst Address Advance AI03649 K Output (1) VV V V tRLKH R V (2) AI03650 K ADD Q0 Q1 L Q2 ADD VALID G tGLQV tBLKH tBHKH B |
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