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AS7341L

I²C Interface

Datasheet

• PUBLIC

DS000718

• v1-00 • 2020-May-25

│ 22

I²C Interface

The device uses I²C serial communication protocol for communication. The device supports 7-bit chip

addressing and both standard and full-speed clock frequency modes. Read and Write transactions

comply with the standard set by Philips (now NXP). Internal to the device, an 8-bit buffer stores the

byte transfer and is retained between transaction events (i.e. valid even after the master issues a

STOP command and the I²C bus is released). During consecutive Read transactions, the

future/repeated I²C Read transaction may omit the memory address byte normally following the chip

address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme

for reading and writing. In general, it is recommended to use I²C bursts whenever possible, especially

in this case when accessing two bytes of one logical entity. When reading these fields, the low byte

must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read

immediately afterwards. When writing to these fields, the low byte must be written first, immediately

followed by the high byte. Reading or writing to these registers without following these requirements

will cause errors.

9.1

I²C Address

Figure 26:

AS7341L I

2C Slave Address

Device

2C Address

AS7341L

0x39

9.2

I²C Write Transaction

A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE,

DATA BYTE(S), and STOP (P). Following each byte (9th clock pulse) the slave places an

ACKNOWLEDGE/NOT- ACKNOWLEDGE (A/N) on the bus. If the slave transmits N, the master may

issue a STOP.

Figure 27:

2C Byte Write

reg_data

WA++

AS7341L 데이터시트(PDF) 23 Page - ams-OSRAM AG