AS7341L datasheet(42/65 Pages) AMSOSRAM

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AS7341L

Datasheet

• PUBLIC

DS000718

• v1-00 • 2020-May-25

│ 41

SP _TH_H_MSB Register (Address 0x87)

Figure 57:

SP _TH_H_MSB Register

Addr: 0x87

SP _TH_H_MSB

Bit

Bit Name

Default

Access

Bit Description

7:0

SP_TH_H_MSB

0x00

Spectral High Threshold MSB

This register provides the high byte of the high

interrupt threshold (CH0).

Both SP_TH_H registers are combined to a 16-bit

threshold. If the value captured by channel 0 is

above the high threshold and the APERS value is

reached the bit SP_IEN is set and an interrupt is

generated.

CFG12 Register (Address 0xB5)

Figure 58:

CFG12 Register

Addr: 0xB5

CFG12

Bit

Bit Name

Default

Access

Bit Description

7:3

reserved

2:0

SP_TH_CH

Spectral Threshold Channel.

Sets the channel used for interrupts, persistence and

the AGC, if enabled, to determine device status and

gain settings.

VALUE

CHANNEL

CH0

CH1

CH2

CH3

CH4

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