AS89010 datasheet(38/43 Pages) AMSOSRAM

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db12348e_V3.11_preliminary_2017-07-06

Page 36 of 41

AS89010

V3.11

// send I2C slave address (R/W=Write)

I2C_Send7bitAddress(I2C_INTERFACE, I2cAddr, I2C_Direction_Transmitter);

// test for completion, TXE, master mode activ, TRA

if(I2cWaitEvent(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) == FALSE)

{

ErrCode = 0x02;

ErrReturn = FALSE;

break;

}

// send register adress

I2C_SendData(I2C_INTERFACE, Addr);

// wait for transmission complete

if(I2cWaitEvent(I2C_EVENT_MASTER_BYTE_TRANSMITTED) == FALSE)

{

ErrCode = 0x04;

ErrReturn = FALSE;

break;

}

// only if Datasize>1: enable ACK

if(Datasize>1)

{

I2C_AcknowledgeConfig(I2C_INTERFACE, ENABLE);

}

// send I2C START

I2C_GenerateSTART(I2C_INTERFACE, ENABLE);

// test for completion

if(I2cWaitEvent(I2C_EVENT_MASTER_MODE_SELECT) == FALSE)

{

ErrCode = 0x05;

ErrReturn = FALSE;

break;

}

// send I2C slave address (R/W=Read)

I2C_Send7bitAddress(I2C_INTERFACE, I2cAddr, I2C_Direction_Receiver);

// MSL, ADDR, BUSY

if(I2cWaitEvent(I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) == FALSE)

{

ErrCode = 0x06;

ErrReturn = FALSE;

break;

}

// data receive loop

while(Datasize > 1)

{

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