AS89010 datasheet(12/43 Pages) AMSOSRAM

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db12348e_V3.11_preliminary_2017-07-06

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AS89010

V3.11

5.1.2 Command Measurement Mode (CMD Mode)

This measurement enables a ‘software start’ of single conversion. Each conversion starts by setting the

SS bit to ‘1’ of OSR register. However, actually start of conversion depends on the chosen Power down

activity. For further details see also Figure 21.

Figure 5: CMD Mode timing with activated Power down

power down

data

fetch

power down

power up

conversion

READY

OUT0..OUT3

TINT

STATE

I²C

activity

start (SS

← ’1')

If Power down has been activated (PD bit in OSR) the conversion starts after the Power-up, approximately

500 µs after the SS bit has been set (Figure 5). Otherwise it starts immediately after delay time defined

by the content of BREAK register which can be configured in 1 µs steps up to 255 µs (Figure 6).

The rising edge of READY signalizes the end of conversion and the output data can be read via the I²C-

Inteface (data fetch). After the conversion, the device returns to the Power down mode or stays active

waiting (idle) for a new action according to the programmed configuration. The conversion time (integration

time TINT) is determined by contents of the register CREGL:T (T).

Figure 6: CMD Mode timing without Power down

idle

conversion

data

fetch

conversion

READY

OUT0..OUT3

TINT

STATE

I²C

activity

start (SS

← ’1')

start (SS

← ’1')

data

fetch

break time

5.1.3 Synchronous Measurement Start Mode (SYNS Mode)

The input pin SYN acts as a trigger event for the conversion start. The falling edge starts the measurement.

The READY pin signalizes the progress of conversion, at rising edge the measurement is stopped and the

current conversion results are stored into output registers. Data fetch should be performed between the

rising edge of READY signal and the next falling edge of SYN in order to allow distortion free measurement.

After the conversion the device changes its state to Standby or stays active waiting (idle), according to

assignment of SB bit (CREGH register). The conversion time (integration time TINT) is determined by the

contents of register CREGL:T (T). For further details see also Figure 22.

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