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db09284e_V3.01_preliminary_2017-07-06

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AS89020

V3.01

7 EXAMPLES OF COMMUNICATION VIA SPI

After a power-up, the device is in the default configuration state. The user can now set up the device for

the application by writing control register. Success of the configuration can be proven by reading the control

register.

Before a measurement can be started, the device must change its state to the measurement state. The

last three bits of OSR:DOS must be loaded with ,011b’. Now a conversion can be started, it will start

accordingly to the falling edge of signal CSN or CONVN after tracking the input signals.

In order to change configuration settings the user has to switch back to the configuration state first.

Some examples of usual SPI communication sequences are shown in the following figures.

a.) Example of Configuration SPI sequences

First of all it is possible to enable the tracking phase (OSR:TRACK = ,1b’)

To show a register read process, the address ,02h’ is chosen (AGEN).

S

WA

WD

RA

X

SDI

S

00h

80h

02h

X

SDO

S

XXh

XXh

XXh

X

During sending the three SDI bytes three SDO bytes are received. In this case these SDO bytes are of no

relevance.

In the next cycle the first received byte on SDO is ,02h’. The following 2 byte are meaningless. The first

transmitted 2 bytes on SDI are always for a “register write” cycle. In the example only a read (SDO) is

relevant. No register write should occur, since this the write address (WA) is ,01h’ (not defined write

register). The write data (WD) in the second byte is meaningless. Since no additional register should be

read, the read address (RA) in byte 3 is also meaningless.

S

WA

WD

RA

X

SDI

S

01h

XXh

XXh

X

SDO

S

02h

XXh

XXh

X

b.) Example of Changing to Measurement State

To proceed the AS89020 switches to the measurement state the OSR:DOS is set to ,03h’. OSR:TRACK is

set to ,1b’ to keep tracking active. After all OSR is set to ,83h’. The read address of third byte at SDI is

meaningless, because of the format change to two bytes during measurement state (see chapter 5.8).

S

WA

WD

RA

X

SDI

S

00h

83h

XXh

X

SDO

S

XXh

XXh

XXh

X

The three SDO bytes are of no relevance.

c.) Example of Measurement SPI sequences

After the last transferred byte at SDI (3rd byte of example b), the next falling edge of the chip select signal

CSN stops the tracking and samples the input signals of all 4 channels. The clock signal SCLK starts the

conversion and also immediately the read out of conversion result byte-by-byte. At the same time the input

stream at SDI for write address WA and write data WD could be for the register OSR with no operation or

no change (WA = ,00h’ and WD = ,00h’). In order to start a new tracking cycle the last data byte WD

should be ,80h’.

S

WA

WD

WA

WD

WA

WD

WA

WD

X

SDI

S

00h

00h

00h

00h

00h

00h

00h

80h

X

SDO

S

CH0[15:0]

CH1[15:0]

CH2[15:0]

CH3[15:0]

X