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db09284e_V3.01_preliminary_2017-07-06

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AS89020

V3.01

PARAMETER

NAME

MIN

TYP

MAX

UNIT

CONDITION

Input High Level

VIH

0.7*VDD

V

Input Low Level

VIL

0.3*VDD

V

Input Hysteresis

VHYST

0.3*VDD

V

Pin CONVN

VDD = 3.3 V

Output High Level

VOH

0.8*VDD

V

ILoad = 1.0 mA

Output Low Level

VOL

0.4

V

ILoad = 1.0 mA

SPI Clock Frequency

fSCLK

0.5

10

16

MHz

up to 10 MHz is re-

commended for

12 Bit accuracy

SPI Setup Time SDI

tSDIS

30

ns

SPI Setup Time CSN

tCSNS

30

2500

ns

min. 2.5 µs is

recommended for

12 Bit accuracy

SPI Hold Time SDI

tSDIH

30

ns

SPI Hold Time CSN

tCSNH

30

ns

SPI Pulse Width CSN

tCSNPW

62.5

ns

Tracking Time3

tTRACK

6

10

µs

Pause Time4

TPAUSESCLK

1/fSCLK

s

recommended for

12 Bit accuracy

Figure 1: SPI Timing

3 The time between two subsequent conversions where bit TRACK = ‚1’ (see 5.2

4 The recommended pause time between two bytes of channel data during the conversation in the measurement state

SCLK

CSN

SDI

tSDIS

tCSNS

tSDIH

BIT5

BIT6

BIT7

tCSNH

BIT7

BIT6

BIT0

BIT1

BIT2

BIT3

BIT4

tCSNPW