CSG14K_CSG8K datasheet(26/114 Pages) AMSOSRAM

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 25

Figure 17:

Power-Up Sequence (not to scale)

Information

The ramp-up of the digital supply (VDD12*) must be done before all the others power

supplies. Guaranty that it is settled and then ramp-up VDD33* and VDDPIX like showed

above.

7.2.3

Clocking

The sensor has two CMOS clock inputs: SPI_CLK and CLK_IN. SPI_CLK is part of the SPI

interface used to configure the sensor. All other internal sensor clocks are derived from the

PLL running on CLK_IN.

Refer to section 5 for the electrical specifications of the input clocks and to section 7.4.3 for

the configuration procedure of the PLL.

7.2.4

SPI and Register Access

The sensor operation must be configured by uploading register settings. These static register

values control the behavior of the sequencer on the chip, but also of all the analog and mixed-

signal blocks. To write and read register settings the SPI interface is used.

The SPI (Serial Peripheral Interface) consists of four wires, as shown in Figure 18.

The CSG14K_CSG8K image sensor always operates as the SPI slave. A single SPI access

always consists of:

●

Transfer of a control bit from master to slave to specify the transfer direction (read or

write).

●

Transfer of 7-bit register address from master to slave.

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