CSG14K_CSG8K datasheet(86/114 Pages) AMSOSRAM

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 85

7.6

Configuring the Output Data Format

7.6.1

Word Alignment

Figure 104:

Training Word Register

Reg. Name

Bank

Addr

Bits

Description

TRAINING_WORD

73-74

[13:0]

See below. Default value is 85

Whenever a data channel is not sending valid data (*), a training word is being transmitted

continuously. The content of the training word can be set with the TRAINING_WORD register.

When the sensor operates in 12-bit mode, only the lowest 12 bits of the register are sent as

training word.

On all DATAx_OUT channels, the last word cycle before DVAL, the training word is inverted.

If the overhead time between two DVAL cycles is only 1 word wide, only the inverted training

word is sent.

(*) Valid data is:

●

DATAx_OUT: Valid pixel data (DVAL = '1')

●

OB_OUT: Valid OB pixel data (OBVAL = '1')

The figure below shows illustrates this timing (drawn in the parallel domain).

Figure 105:

Training Pattern

When the sensor is not transmitting valid data, the training word can be used by the external

controller to do word alignment (in other words: finding the position of bit [0]). Detecting the

inverted training word will alert the presence of valid pixel data 1 pixel cycle in advance.

When the sensor is IDLE, all control word bits except the LSB (SYNC) are '0'. Detecting the

SYNC bit allows for easy word alignment at the receiver side.

7.6.2

Outputs

As illustrated in Figure 52 the sensor has 8 output channels on each side to transfer valid

image data. This means that in the fastest configuration, the sensor can output 16 pixels at

DVAL

DATAx_OUT

...

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