R7KA8M2AFDCAM datasheet(289/295 Pages) RENESAS

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Table A3.2

Access cycles (2 of 3)

Peripheral base

address symbol

Address*1

Number of access cycles

ICLK = PCLK

ICLK > PCLK*2

Cycle

unit

Related function

From

Read

Write

Read

Write

CRC, DOC

0x4031_0000

0x4031_1FFF 4

2 to 4

1 to 3

PCLKA

CRC Calculator, Data

Operation Circuit

GPT32n,

GPT_OPS

0x4032_2000

0x4032_3F0F

7 to 9

4 to 6

PCLKA

General PWM 32-Bit

Timer n, Output Phase

Switching Controller

GPT_GTCLK

0x4032_3F10

0x4032_3F1F

2 to 4

1 to 3

PCLKA

General PWM Timer

Clock Control

PDG

0x4032_4000

0x4032_4FFF 3

1 to 3

0 to 2

PCLKA

PWM Delay

Generation Circuit

ADC_B

0x4033_8000

0x4034_7FFF 4

2 to 4

1 to 3

PCLKA

A/D Converter

CEU

0x4034_8000

0x4034_FFFF 7

5 to 7

3 to 5

PCLKA

Capture Engine Unit

USBHS*3

0x4035_1000

0x4035_115F

BWAIT+4

BWAIT+3

(BWAIT+2

) to

(BWAIT+4

)

(BWAIT+1

) to

(BWAIT+3

)

PCLKA

USB 2.0 High-Speed

Module

USBHS*3

0x4035_1160

0x4035_1167

BWAIT+4

130

(BWAIT+2

) to

(BWAIT+4

)

128 to 130 PCLKA

USB 2.0 High-Speed

Module

USBHS

0x4035_1168

0x4035_116F

130

6 to 8

128 to 130 PCLKA

USB 2.0 High-Speed

Module

SCIn, SPIn, I3C

0x4035_8000

0x4035_FFFF 4

2 to 4

1 to 3

PCLKA

Serial Communication

Interface n, Serial

Peripheral Interface n,

I3C Bus Interface

ECCMBn

0x4036_F200

0x4036_F3FF 5

3 to 5

2 to 4

PCLKA

Error correction circuit

for MBRAMn

CANFDn

0x4038_0000

0x4038_3FFF 4

2 to 4

1 to 3

PCLKA

CANFD Module n

ESWM

0x403C_0000 0x403E_FFFF —

—

7 to 12

2 to 4

PCLKA

Layer 3 Ethernet

Switch Module

PORTn

0x4040_0000

0x4040_01FF

ICLK

Port n Control

Registers

PFS

0x4040_0800

0x4040_0FFF 8

ICLK

Pmn Pin Function

Control Register

RSIP-E50D

3 to 5

1 to 6

0 to 2

PCLKA

Renesas Secure IP

Table A3.2

Access cycles (3 of 3)

Peripheral base

address symbol

Address*1

Number of access cycles

ICLK = MRPCLK

ICLK > MRPCLK*2

Cycle

unit

Related function

From

Read

Write

Read

Write

MRAM

0x4013_0000

0x4013_FFFF 4

2 to 4

1 to 3

MRPCLK

MRAM control

Note 1. This table only shows secure address. Access cycle of the non-secure address is the same as its secure address.

Note 2. If the number of PCLK or MRPCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the

maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3.

Note 3. BWAIT is the number of waits (not cycles) described in the USBHS.BUSWAIT register.

RA8M2 Datasheet

Appendix 3. I/O Registers

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 289 of 295

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