R7KA8M2AFDCAM datasheet(292/295 Pages) RENESAS

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Revision History

Revision 1.00— February 14, 2025

First edition, issued

Revision 1.10 — May 16, 2025

1. Overview:

● Updated Figure 1.2 Part numbering scheme.

2. Electrical Characteristics:

● Updated 2. Electrical Characteristics.

● Updated 2.1 Absolute Maximum Ratings.

● Updated 2.2.5 Operating and Standby Current.

● Updated 2.3.10 SPI Timing.

● Updated 2.3.11 OSPI Timing.

● Updated 2.6 ADC Characteristics.

● Added 2.11 External VDD timing Characteristics.

Appendix:

● Updated Figure A2.3 HLQFP 176-pin in Appendix 2.

● Updated Table A5.1 Module name vs peripheral variant in Appendix 5.

Revision 1.20 — Jul 31, 2025

1. Overview:

● Updated Table 1.8 Communication interfaces

● Updated Table 1.15 Pin functions

● Updated Table 1.16 Pin list for the Standard product

● Updated Table 1.17 Pin list for the SiP product

2. Electrical Characteristics:

● Updated Table 2.16 Current of high-speed mode, maximum data processing, CPU0 Deep Sleep, CPU1 active, peripheral clock ON

(DCDC mode)

● Updated Table 2.18 Current of high-speed mode, maximum data processing (MVE operation), peripheral clock OFF (DCDC mode)

● Updated Table 2.19 Current of high-speed mode, maximum data processing (MVE operation), peripheral clock OFF (External VDD

mode)

● Updated Table 2.20 Current of high-speed mode, maximum data processing (MVE operation), CPU0 active, CPU1 Deep Sleep,

peripheral clock OFF (DCDC mode)

● Updated Table 2.21 Current of high-speed mode, maximum data processing (MVE operation), CPU0 active, CPU1 Deep Sleep,

peripheral clock OFF (External VDD mode)

● Updated Table 2.22 Current of high-speed mode, maximum data processing, CPU0 Deep Sleep, CPU1 active, peripheral clock OFF

(DCDC mode)

● Updated Table 2.23 Current of high-speed mode, maximum data processing, CPU0 Deep Sleep, CPU1 active, peripheral clock OFF

(External VDD mode)

● Updated Table 2.24 Current of high-speed mode, CPU Sleep mode (DCDC mode)

● Updated Table 2.26 Current of high-speed mode, CPU0 Sleep, CPU1 Deep Sleep (DCDC mode)

● Updated Table 2.28 Current of high-speed mode, CPU0 Deep Sleep, CPU1 Sleep (DCDC mode)

● Updated Table 2.30 Current of high-speed mode, CPU Deep Sleep mode (DCDC mode)

Revision 1.30 — Feb 27, 2026

1. Overview:

● Updated Figure 1.2 Part numbering scheme

● Updated Table 1.13 Product list

● Updated Table 1.14 Function Comparison

● Updated Table 1.15 Pin functions

● Added Figure 1.5 Pin assignment for BGA 169-pin

● Updated Figure 1.6 Pin assignment for BGA 303-pin

● Updated Table 1.16 Pin list for the Standard product

● Updated Table 1.17 Pin list for the SiP product

●

RA8M2 Datasheet

Revision History

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 292 of 295

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