R7KA8M2AFDCAM datasheet(195/295 Pages) RENESAS

195 / 295 page

Note 5. On a Legacy Bus where I2C Devices need to see Start

Note 6. Slaves that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3

Note 7. On a Mixed Bus with Fm Legacy I2C Devices, tAVAL is 300 ns shorter than the Fm Bus Free Condition time (tBUF)

Table 2.72

I3C timing (Push-Pull Timing Parameters for SDR and HDR-DDR Modes)

Setting of the I3C_SCL0, I3C_SDA0 pins are not required with the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

VCC

Min

Max

Unit

Test

condition

I3C Push-

Pull

Timing

Parameter

s for SDR

and HDR-

DDR

Modes

SCL Clock Frequency

fSCL*1

3.00 V or above

0.01

12.5

MHz —

1.65 to 1.95 V

0.01

12.5

SCL Clock Low Period

tLOW

3.00 V or above

—

Figure

2.91

1.65 to 1.95 V

—

tDIG_L*2 *4

3.00 V or above

—

Figure

2.91

1.65 to 1.95 V

—

SCL Clock High Period for

Mixed Bus

tHIGH_MIXE

3.00 V or above

—

Figure

2.91

1.65 to 1.95 V

—

tDIG_H_MIX

*2 *3

3.00 V or above

Figure

2.91

1.65 to 1.95 V

SCL Clock High Period

tHIGH

3.00 V or above

—

Figure

2.91

1.65 to 1.95 V

—

tDIG_H*2

3.00 V or above

—

Figure

2.91

1.65 to 1.95 V

—

Clock in to Data Out for Slave tSCO

3.00 V or above

—

Figure

2.96

1.65 to 1.95 V

—

SCL Clock Rise Time

tCR

3.00 V or above

—

150 × 1 /

fSCL (capped at

60)

Figure

2.91

1.65 to 1.95 V

—

150 × 1 /

fSCL (capped at

60)

SCL Clock Fall Time

tCF

3.00 V or above

—

150 × 1 /

fSCL (capped at

60)

Figure

2.91

1.65 to 1.95 V

—

150 × 1 /

fSCL (capped at

60)

SDA Signal Data

Hold in Push-Pull

Mode

Master

tHD_PP*4*5 3.00 V or above

tCR + 3 and tCF + 3

—

Figure

2.95

1.65 to 1.95 V

tCR + 3 and tCF + 3

—

Slave

tHD_PP*5

3.00 V or above

—

Figure

2.95

1.65 to 1.95 V

—

SDA Signal Data Setup in

Push-Pull Mode

tSU_PP

3.00 V or above

N/A

Figure

2.97

1.65 to 1.95 V

N/A

Clock After Repeated START

(Sr)

tCASr

3.00 V or above

tCASmin

N/A

Figure

2.99

1.65 to 1.95 V

tCASmin

N/A

Clock Before Repeated

START (Sr)

tCBSr

3.00 V or above

tCASmin / 2

N/A

Figure

2.99

1.65 to 1.95 V

tCASmin / 2

N/A

Capacitive Load per Bus Line

(SDA/SCL)

3.00 V or above

—

1.65 to 1.95 V

—

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 195 of 295

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