R7KA8M2AFDCAM datasheet(196/295 Pages) RENESAS

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Note 1. fSCL = 1 / (tDIG_L + tDIG_H)

Note 2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH.

Note 3. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure that

I2C Devices do not interpret I3C signaling as valid I2C signaling.

Note 4. As both edges are used, the hold time needs to be satisfied for the respective edges; i.e., tCF + 3 for falling edge clocks, and tCR + 3

for rising edge clocks.

Note 5. In SDR Mode the Hold time parameter is referred to as tHD_SDR, and in DDR Mode it is referred to as tHD_DDR.

Table 2.73

I3C timing (Push-Pull Timing Parameters for HDR-TSP and HDR-TSL Modes)

Setting of the I3C_SCL0, I3C_SDA0 pins are not required with the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

VCC

Min

Max

Unit

Test

conditions

I3C Push-Pull

Timing

Parameters for

HDR-TSP and

HDR-TSL

Modes

Edge-to-Edge

Period

tEDGE*1 *2

3.00 V or above

tDIG_H

—

Figure 2.101

1.65 to 1.95 V

tDIG_H

—

Allowed

Difference

Between

Signals for

‘Simultaneous’

Change

tSKEW

3.00 V or above

—

1.65 to 1.95 V

—

Stable

Condition

Between

Symbols

tEYE

3.00 V or above

—

1.65 to 1.95 V

—

Time Between

Successive

Symbols

tSYMBOL

3.00 V or above

tEDGE Min

—

1.65 to 1.95 V

tEDGE Min

—

Symbol Clock

tCLOCK

3.00 V or above

1 / fSCL (Max)

—

1.65 to 1.95 V

1 / fSCL (Max)

—

Note 1. Edges occur at the rate of 1 / (tEDGE × 2)

Note 2. In a Mixed Bus, HDR-TSL shall respect the maximum tDIG_H_MIXED shown in Figure 2.94.

0.7×VCC

0.3×VCC

tCR

tCF

tHIGH

tDIG_H

tLOW

tDIG_L

Figure 2.91

tDIG_H and tDIG_L

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 196 of 295

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