R7KA8M2AFDCAM datasheet(213/295 Pages) RENESAS

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2.3.19

ESWM Timing

Table 2.79

ESWM timing (RMII)

Conditions:

1. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: ETn_MDC, ETn_MDIO.

2. The drive capacity selection and voltage range for pins other than ETn_MDC, ETn_MDIO.

● RMII use: High drive select, VCC = 2.7 to 3.6

Parameter

Symbol

VCC

Min

Max

Unit

Test

conditions

ESWM (RMII)

RMIIn_REF50CK cycle time

Tck

2.70V or

above

—

Figure 2.112

RMIIn_REF50CK frequency, typical 50 MHz

—

50 + 100

ppm

MHz

RMIIn_REF50CK duty

—

RMIIn_REF50CK rise/fall time

Tckr/ckf

0.5

3.5

RMIIn_xxxx*1 output delay

Tco

2.5

RMIIn_xxxx*2 setup time

Tsu

—

RMIIn_xxxx*2 hold time

Thd

—

RMIIn_xxxx*1 *2 rise/fall time

Tr/Tf

0.5

Note 1. RMIIn_TX_EN, RMIIn_TXD1, RMIIn_TXD0.

Note 2. RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER.

Change in

signal level

Signal

Thd

Tsu

Tco

Tckr

Tckf

Tck

Signal

90%

50%

10%

70%

50%

RMIIn_REF50CK

RMII_xxxx*1

30%

Change

in signal

level

Change

in signal

level

Note 1. RMIIn_TX_EN, RMIIn_TXD1, RMIIn_TXD0, RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER

Figure 2.112

RMIIn_REF50CK and RMII signal timing

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 213 of 295

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