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Table 2.81

ESWM timing (GMII)

Conditions:

1. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: ETn_MDC, ETn_MDIO.

2. The drive capacity selection and voltage range for pins other than ETn_MDC, ETn_MDIO.

● GMII use at 2.5 V: RGMII 2.50V drive select, VCC = 2.3 to 2.7

● GMII use at 3.3 V: RGMII 3.30V drive select, VCC = 3.0 to 3.6

Parameter

Symbol

VCC

Min

Max

Unit

Test

conditions

ESWM (GMII) ETn_GTX_CLK Frequency

tFREQ

2.30 V to 3.60

125 - 100 ppm 125 + 100

ppm

MHz

Figure 2.115

Figure 2.116

ETn_GTX_CLK Period

tPERIOD

7.5

8.5

ETn_RX_CLK Period

tPERIOD

7.5

—

ETn_GTX_CLK, ETn_RX_CLK

Time High

tHIGH

2.5

—

ETn_GTX_CLK, ETn_RX_CLK

Time Low

tLOW

2.5

—

ETn_GTX_CLK, ETn_RX_CLK

Rise Time

—

ETn_GTX_CLK, ETn_RX_CLK

Fall Time

—

Magnitude of ETn_GTX_CLK,

ETn_RX_CLK Slew Rate

(rising)*1

—

0.6

—

V/ns

Magnitude of ETn_GTX_CLK,

ETn_RX_CLK Slew Rate

(falling)*1

—

0.6

—

V/ns

ETn_TXD, ETn_TX_EN,

ETn_TX_ER Setup to

↑ETn_GTX_CLK and

ETn_RXD, ETn_RX_DV,

ETn_RX_ER Setup to ↑

ETn_RX_CLK

tSETUP

2.5

—

ETn_TXD, ETn_TX_EN,

ETn_TX_ER Hold from

↑ ETn_GTX_CLK and

ETn_RXD, ETn_RX_DV,

ETn_RX_ER Hold from ↑

ETn_RX_CLK

tHOLD

0.5

—

ETn_TXD, ETn_TX_EN,

ETn_TX_ER Setup to

↑ ETn_GTX_CLK and

ETn_RXD, ETn_RX_DV,

ETn_RX_ER Setup to ↑

ETn_RX_CLK

tSETUP(RCVR)

—

TXD, TX_EN, TX_ER,

ETn_TX_ER Hold from ↑

GTX_CLK and RXD, RX_DV,

RX_ER Hold from ↑ RX_CLK

tHOLD(RCVR)

—

Note 1. Clock Skew rate is the instantaneous rate of change of the clock potential with respect to time (dV/dt), not an average value

over the entire rise or fall time interval. Conformance with this specification guarantees that the clock signals will rise and fall

monotonically through the switching region.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

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