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WM8959 데이터시트(PDF) 82 Page - Wolfson Microelectronics plc

부품명 WM8959
상세설명  Mobile Multimedia DAC with Dual-Mode Class AB/D Speaker Driver
PDF  155 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8959 데이터시트(HTML) 82 Page - Wolfson Microelectronics plc

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WM8959
Pre-Production
w
PP, May 2008, Rev 3.1
82
INTERRUPT EVENT OUTPUT
An interrupt can be generated by any of the following events described earlier:
•
Button Control input (on GPIO1, GPIO3 to GPIO5, GPI7 and GPI8)
•
MICBIAS current / short circuit / accessory detect
•
PLL Lock
•
Temperature Sensor
The interrupt status flag IRQ is asserted when any un-masked Interrupt input is asserted. It is the
OR’d combination of all the un-masked Interrupt inputs. If required, this flag may be inverted using
the IRQ_INV register bit. The GPIO pins can be configured to output the IRQ signal.
The interrupt behaviour is driven by level detection (not edge detection) of the un-masked inputs.
Therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt
status flag IRQ will be triggered again even though no transition has occurred. If edge detection is
required (eg. confirming that the input has been de-asserted), then the polarity inversion may be
used after each event in order to detect each rising and falling edge separately. This is described
further in the “GPIO Summary” section.
The status of the IRQ flag may be read back via the control interface. The status of each GPIO pin
and the internal signals PLL_LCK, TEMPOK, MICSHRT and MICDET may also be read back in the
same way.
The IRQ register (R18) is described in Table 47. The status of the GPIO pins or other Interrupt inputs
can be read back via the read/write bits R18[11:0]. The Interrupt inputs are latched once set. Each
input may be reset by writing a 1 to the appropriate bit. The IRQ bit cannot be reset; it is the OR’d
combination of all other registers and will reset only if R18[11:0] are all 0.
If direct output of the Interrupt signal is required to external pins of the WM8959, the following
register settings are required:
•
GPIO1_ENA = 1 (only required if using GPIO1)
•
AIF_SEL = 0 (only required if using GPIO3, GPIO4 or GPIO5)
•
AIF_TRIS = 0
•
GPIOn_SEL = 0111 for the selected Interrupt (IRQ) output pin
•
GPIOn_PU = 0 for the selected Interrupt (IRQ) output pin
•
GPIOn_PD = 0 for the selected Interrupt (IRQ) output pin



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