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WM8959 데이터시트(PDF) 28 Page - Wolfson Microelectronics plc |
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WM8959 데이터시트(HTML) 28 Page - Wolfson Microelectronics plc |
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28 / 155 page ![]() WM8959 Pre-Production w PP, May 2008, Rev 3.1 28 AUDIO INTERFACE TIMING – SLAVE MODE Figure 6 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK (or BCLK2) cycle time tBCY 50 ns BCLK (or BCLK2) pulse width high tBCH 20 ns BCLK (or BCLK2) pulse width low tBCL 20 ns DACLRC (or DACLRC2) set-up time to BCLK (or BCLK2) rising edge tLRSU 20 ns DACLRC (or DACLRC2) hold time from BCLK (or BCLK2) rising edge tLRH 10 ns DACDAT (or DACDAT2) hold time from BCLK (or BCLK2) rising edge tDH 10 ns DACDAT (or DACDAT2) set-up time to BCLK (or BCLK2) rising edge tDS 20 ns Note: BCLK (or BCLK2) period should always be greater than or equal to MCLK period. |
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