PSD835G2-90UI datasheet(39/110 Pages) STMICROELECTRONICS

39 / 110 page

PSD8XX Family

PSD835G2

The

PSD835G2

Functional

Blocks

(cont.)

9.2.2.1 Output Micro

⇔Cell

Eight of the Output Micro

⇔Cells are connected to Port A pins are named as McellA0-7.

The other eight Micro

⇔Cells are connected to Port B pins are named as McellB0-7.

Maximum

Native

Borrowed

Data Bit for

Output

Port

Product

Loading or

Micro

⇔Cell

Assignment

Terms

Reading

McellA0

Port A0

McellA1

Port A1

McellA2

Port A2

McellA3

Port A3

McellA4

Port A4

McellA5

Port A5

McellA6

Port A6

McellA7

Port A7

McellB0

Port B0

McellB1

Port B1

McellB2

Port B2

McellB3

Port B3

McellB4

Port B4

McellB5

Port B5

McellB6

Port B6

McellB7

Port B7

Table 13. Output Micro

⇔Cell Port and Data Bit Assignments

The Output Micro

⇔Cell (OMC) architecture is shown in Figure 13. As shown in the figure,

there are native product terms available from the AND array, and borrowed product terms

available (if unused) from other OMCs. The polarity of the product term is controlled by the

XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or

combinatorial logic. The multiplexer selects between the sequential or combinatorial logic

outputs. The multiplexer output can drive a Port pin and has a feedback path to the AND

array inputs.

The flip-flop in the OMC can be configured as a D, T, JK, or SR type in the PSDsoft

program. The flip-flop’s clock, preset, and clear inputs may be driven from a product term

of the AND array. Alternatively, the external CLKIN signal can be used for the clock input

to the flip-flop. The flip-flop is clocked on the rising edge of the clock input. The preset and

clear are active-high inputs. Each clear input can use up to two product terms.

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