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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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NRF52810-QCAA-R 데이터시트(PDF) 67 Page - Nordic Semiconductor |
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NRF52810-QCAA-R 데이터시트(HTML) 67 Page - Nordic Semiconductor |
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67 / 483 page  Power and clock management Register Offset Description GPREGRET2 0x520 General purpose retention register DCDCEN 0x578 DC/DC enable register RAM[0].POWER 0x900 RAM0 power control register RAM[0].POWERSET 0x904 RAM0 power control set register RAM[0].POWERCLR 0x908 RAM0 power control clear register RAM[1].POWER 0x910 RAM1 power control register RAM[1].POWERSET 0x914 RAM1 power control set register RAM[1].POWERCLR 0x918 RAM1 power control clear register RAM[2].POWER 0x920 RAM2 power control register RAM[2].POWERSET 0x924 RAM2 power control set register RAM[2].POWERCLR 0x928 RAM2 power control clear register RAM[3].POWER 0x930 RAM3 power control register RAM[3].POWERSET 0x934 RAM3 power control set register RAM[3].POWERCLR 0x938 RAM3 power control clear register RAM[4].POWER 0x940 RAM4 power control register RAM[4].POWERSET 0x944 RAM4 power control set register RAM[4].POWERCLR 0x948 RAM4 power control clear register RAM[5].POWER 0x950 RAM5 power control register RAM[5].POWERSET 0x954 RAM5 power control set register RAM[5].POWERCLR 0x958 RAM5 power control clear register RAM[6].POWER 0x960 RAM6 power control register RAM[6].POWERSET 0x964 RAM6 power control set register RAM[6].POWERCLR 0x968 RAM6 power control clear register RAM[7].POWER 0x970 RAM7 power control register RAM[7].POWERSET 0x974 RAM7 power control set register RAM[7].POWERCLR 0x978 RAM7 power control clear register Table 15: Register Overview 5.3.9.1 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description A RW POFWARN Write '1' to Enable interrupt for POFWARN event See EVENTS_POFWARN Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled B RW SLEEPENTER Write '1' to Enable interrupt for SLEEPENTER event See EVENTS_SLEEPENTER Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled C RW SLEEPEXIT Write '1' to Enable interrupt for SLEEPEXIT event See EVENTS_SLEEPEXIT Set 1 Enable Disabled 0 Read: Disabled 4430_161 v1.0 67 |
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