STB5701

Functional description

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The A-counter configuration represents the lower bits in the feedback divider register and

the upper bits the M-counter configuration respectively. According to that, the following

counter ranges are implemented:

0

7

and therefore the range of the overall feedback divider ratio results in:

56

The user does not need to care about the A- and M-counter settings. It is only necessary to

know the overall feedback divider ratio N to program the register settings.

4.2.2

Reference divider

The reference divider reduces the frequency of the external crystal (FXTAL) to an internal

reference frequency (FR) used for the phase-locked loop.

This value, corresponding to the channel step, it is set by programming a 10-bit counter

through the I2C interface (PINs 12, 13).

Therefore the range of the Reference divider ratio is:

0

4.2.3

Phase Frequency Detector

The phase detector (PFD) is a device that compares two input (fN and fR) phases,

generating an output that is a measure of their phase difference.

The gain of the phase detector can be expressed as:

where ICP is the charge pump current.

If fR doesn't equal fN, the phase-error signal, after being filtered and amplified, causes the

VCO frequency to deviate in the direction of fR.